1. Field of the Invention
The present invention relates to a semiconductor memory device. More particularly, it relates to a semiconductor memory device which simplifies an input/output control logic by controlling a decoding sequence of a sub-cell block mounted into a cell array.
2. Description of the Prior Art
One bank is divided into m cell arrays on the basis of a word line WL as shown in FIG. 1A showing a general core block, each cell array is divided into n sub-cell blocks on the basis of a column line Yi as shown in FIG. 1B showing an internal structure of a cell array of FIG. 1A.
A bit line sense-amp BLSA is positioned at the upper and lower parts of each sub-cell block. A sub-row decoder sub.sub.-- xdec is positioned between the sub-cell blocks. A sub-hole block is positioned at the upper and lower parts of the sub-row decoder sub.sub.-- xdec.
According to the above bank structure, a cell data is loaded on a bit line by an enabled word line WL, and is amplified by a bit line sense-amp BLSA.
After that, if a read command or a write command is input, a column address is received, the column address is then decoded, so that a corresponding column line Yi is enabled. The data connected to an enabled column line Yi is only passed and then loaded on an input/output (hereinafter referred to as IO) line. In this case, a structure of the input/output (IO) line is the same as FIG. 2.
FIG. 2 illustrates a structure of a general input/output (IO) line.
Referring to FIG. 2, the data loaded on a segment input/output (hereinafter referred to as SIO) line 10 positioned at the upper and lower parts of a cell array by a column line Yi is again loaded on a local input/output (hereinafter referred to as LIO) line 12 in both sub-hole blocks. The data is transmitted to an input/output sense-amp IOSA mounted into an input/output control circuit 14 in a bank control block. An output data of the input/output sense-amp IOSA is loaded on a global input/output (GIO) line 16. In a writing operation, a data of a global line is input to a write driver mounted into the input/output control circuit 14 in a bank control block, and is then loaded on the local input/output (LIO) line 12.
Here, the reference numeral 14 indicates a block including both the input/output sense-amp IOSA and the write driver WD. In the present invention, the input/output sense-amp IOSA and the write driver WD are called an input/output (IO) control circuit.
As stated above, since one cell array is divided into n sub-cell blocks, the number of the input/output sense-amps (IOSAs) is n+1. Since a plurality of global input/outputs (GIOs) being an output of each input/output sense-amp IOSA are at the same line, only two input/output sense-amps IOSAs on which data is loaded by a column line Yi should be enabled.
A decoding input address of selecting a sub-cell block having the enabled column line Yi is needed as an input of an input/output sense-amp (IOSA) enable logic. The input/output sense-amp (IOSA) enable logic is mounted into the input/output sense-amp IOSA & write driver block 14.
For example, as shown in FIG. 3 illustrating a general sub-cell block decoding, assuming that the number of sub-cell blocks is 8 on the basis of the column line Yi, the number of column addresses for a block selection is 3. These three column addresses are determined as A5, A6 and A7, respectively.
If a decoding sequence of the column addresses A5, A6 and A7 of a sub-cell block is determined as a sequence from 0 to 7 (i.e., 0-&gt;1-&gt;2-&gt;3-&gt;4-&gt;5-&gt;6-&gt;7), a combination of the column addresses A5, A6 and A7 for enabling each of nine input/output sense-amps (IOSAs) is as follows.
First, an input/output sense-amp IOSA&lt;0&gt; is enabled only under the condition that a decoding of the column addresses A5,A6 and A7 is "0" (i.e., A5("L"), A6("L") and A7("L")). Namely, as shown in FIG. 4A, a logic for enabling the input/output sense-amp IOSA&lt;0&gt; enables a corresponding input/output sense-amp IOSA&lt;0&gt; by using a NAND gate N1 performing a NAND operation about three inputs A5b, A6b and A7b. In addition, a structure of another input/output sense-amp IOSA&lt;8&gt; is identical with that of the input/output sense-amp IOSA&lt;0&gt;.
An input/output sense-amp IOSA&lt;1&gt; should be enabled under the condition that the column addresses A5, A6 and A7 are "0"(i.e., A5("L"), A6("L") and A7("L")) and "1"(i.e., A5("L"), A6("L") and A7("H")). Accordingly, as shown in FIG. 4B, the column addresses A5 and A6 of "L" are used as an input of an enable logic of the input/output sense-amp IOSA&lt;1&gt;, and the other column address A7 is disregarded. A NAND gate N2 performing a NAND operation about the column addresses A5 and A6 enables a corresponding input/output sense-amp IOSA&lt;1&gt;.
Other input/output sense-amps IOSA&lt;1&gt;, IOSA&lt;3&gt;, IOSA&lt;5&gt; and IOSA&lt;7&gt; also achieve a logic by using the column addresses A5 and A6 without using the column address A7.
The input/output sense-amp IOSA&lt;2&gt; should be enabled only under the condition that the column addresses A5, A6 and A7 are "1"(i.e., A5("L"), A6("L") and A7("H")) and "2"(i.e., A5 ("L"), A6("H") and A7("L")), so that the input/output sense-amp IOSA&lt;2&gt; is enabled under the condition that the column address AS is "L" and the other column addresses A6 and A7 are either "L,H" or "H,L".
Accordingly, as shown in FIG. 4C, an enable logic of the input/output sense-amp IOSA&lt;2&gt; enables a corresponding input/output sense-amp IOSA&lt;2&gt; by using a plurality of input lines and a plurality of NAND gates N3, N4, N5 and N6. Also, the number of input lines of an input/output sense-amp IOSA&lt;6&gt; is identical with the number of input lines of the input/output sense-amp IOSA&lt;2&gt;.
In case of an input/output sense-amp IOSA&lt;4&gt;, the input/output sense-amp IOSA&lt;4&gt; should be enabled under the condition that the column addresses A5, A6 and A7 are "L, H, H" and "H, L, L". Accordingly, as shown in FIG. 4D, the enable logic employs a plurality of input lines, a plurality of NAND gates N7, N8 and N9, and an inverter IV1.
As stated above, in case of decoding k addresses in order to enable only one sub-cell block among n sub-cell blocks, all of the k addresses should be needed as an input of the input/output (IO) control circuit, thereby requiring a complicated circuit and enlarging a layout area.